1. Field of the Invention
The present invention relates to a clock generating circuit, and in particular, to a clock generating circuit for modulating a frequency for spectrum spread by controlling the phase difference between a reference clock and an output clock at high accuracy, and a method for controlling the same.
2. Description of the Related Art
In recent years, a spectrum spread clock generator (hereinafter also called an “SSCG”) has been spotlighted, which reduces EMI (Electro Magnetic Interference) noise. The SSCG is provided with a PLL circuit and spreads a frequency spectrum of an output clock signal by locking the frequency for the reference clock with respect to the output clock signal and modulating the frequency.
Since an efficient countermeasure can be taken for the EMI noise if the SSCG is utilized, it is highly demanded that utilization of the SSCG is enabled even for devices for which it has been difficult to utilize the SSCG before.
As an example, a case where the SSCG is utilized for a synchronous interface which carries out data transfer between two flip-flops in synchronization with a clock signal is taken into consideration. In this case, it is assumed that a system clock signal (reference clock signal in the SSCG) is connected to the clock end of the output side flip-flop, and an output clock signal of the SSCG is connected to the clock end of the input side flip-flop. A phase difference between the system clock signal and the SSCG output clock signal changes from time to time due to modulation of the SSCG frequency. Therefore, if the phase difference exceeds one cycle, such a situation occurs, in which data outputted from the output side flip-flop are not taken into the input side flip-flop. Accordingly, in a case where the SSCG is thus utilized in the synchronous interface, it is necessary that the modulation of frequency of the SSCG is controlled so that the phase difference of respective clock signals does not exceed the length of one cycle of the system clock signal. That is, it is required that the frequency modulation is controlled with the phase difference of the reference clock and output clock signals kept at high accuracy with respect to the SSCG.
A clock generating circuit disclosed by Japanese Unexamined Patent Publication No. 2005-20083 has been proposed to meet such a demand. The clock generating circuit according to Japanese Unexamined Patent Publication No. 2005-20083 is provided, as depicted in FIG. 11, with a delay element that delays an oscillation clock signal (hereinafter also called an “output clock signal”) and generates a plurality of delay clock signals the respective phases of which differ from each other, and a selector circuit for selecting one of the plurality of delay clock signals and outputting an internal clock. In the selector circuit, frequency modulation is carried out for spectrum spread by switching the delay clock signal.
Also, in the clock generating circuit, a range of fluctuations in delay time in the delay element is controlled so as to be accommodated in one cycle of the output clock signal. Therefore, it is possible to carry out frequency modulation by controlling the phase difference between the reference clock signal and output clock signal at high accuracy.